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preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 1 copyright ? cirrus logic, inc. 2000 (all rights reserved) p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.cirrus.com CS98000 internet dvd (idvd) chip solution features l powerful dual 32-bit riscs >160mips l software based on popular rtos, c/c++ l mpeg video decoder supports dvd, vcd, vcd 3.0, svcd standards l video input with picture-in-picture & zoom l 8-bit multi-region osd w/vertical flicker filter l universal subpicture unit for dvd and svcd l pal<->ntsc scaling ~ transcoding l supports sdram and flash memories l powerful 32-bit audio dsp >80 mips l decodes: 5.1 channel ac-3, mpeg stereo l plays mp-3 cds (a mp-3 cd =12 albums) l karaoke echo mix and pitch shift l optional 3-d virtual, bass & treble control l 8-channel dual-zone pcm output l iec-60958/61937 out: ac-3, dts, mpeg l multi-mode serial audio i/o: i2s & ac-link l av bus or atapi interface or dvd/cd/hd l gpio support for all common sub-circuits description overall the CS98000 crystal dvd processor is targeted as a market specific consumer entertainment processor empowering new product classes with the inclusion of a dvd player as a fundamental feature. this integrated circuit when used with all the other crystal mixed signal data converters, dsps and high quality factory firmware enables the conception and rapid design of market lead- ing internet age products like: ? dvd a/v mini-system ? home media controller ? combination dvd player ? car/suv entertainment unit future firmware enhancements: ? web i/o via ac-link input & built-in soft modem ? dvd audio navigation ? mlp decoder, dts decoder, aac decoder ? mp-3 encoder, ripping controller ordering information CS98000-cq 0 to 70 c 208-pin cs98010-cq 0 to 70 c 128-pin memory controller sdram control flash control risc-1 i-cache d-cache mmu mac risc-2 i-cache d-cache mmu mac mpeg decoder vlc parser idct ram moco dataflow engine dma / bitblit sram buffer subpicture decode scaler video input filter scaler video processor on-screen display picture-in-picture video/graphics display audio i/o pcm out pcm in xmt958 registers stc interrupts system controls clock manager external i/os remote input gpios sdram a/v bus atapi-ide local bus 32- bit dsp cpu / mac i-cache x,y data memory dec 00 ds525pp1
CS98000 2 ds525pp1 table of contents 1. characteristics and specifications ........................................................................ 4 1.1 ac electrical specifications .............................................................................................. .4 1.1.1 atapi interface ..................................................................................................... 4 atapi transaction............................................................................................................. 4 1.1.2 sdram interface .................................................................................................. 5 1.1.3 video interface ...................................................................................................... 7 CS98000 with video encoder.......................................................................................... 7 1.2 dc electrical specification ............................................................................................... .. 8 absolute maximum rating.............................................................................................. 8 electrical characteristics......................................................................................... 8 2. typical application ....................................................................................................... ... 9 3. functional description ............................................................................................... 10 3.1 block diagram ............................................................................................................. ..... 10 3.2 CS98000 device details .................................................................................................. 10 3.2.1 risc-32 .............................................................................................................. 10 3.2.2 dsp-32 ................................................................................................................ 10 3.2.3 system controls .................................................................................................. 10 3.2.4 memory controller ............................................................................................... 11 3.2.5 data flow engine ................................................................................................ 11 3.2.6 mpeg video decoder ......................................................................................... 11 3.2.7 system synchronization ...................................................................................... 11 3.2.8 audio interface .................................................................................................... 11 3.2.9 video input .......................................................................................................... 11 3.2.10 external interface .............................................................................................. 11 3.2.11 video processor ................................................................................................ 11 3.2.12 sub-picture processor ....................................................................................... 12 3.2.13 system functions .............................................................................................. 12 3.3 risc processor ............................................................................................................ ... 12 3.4 dsp processor ............................................................................................................. ... 12 3.5 memory control ............................................................................................................ ... 12 3.6 dataflow control (dma) ................................................................................................... 1 3 3.7 system control functions ................................................................................................ 13 3.8 dvd/atapi interface ....................................................................................................... 13 3.9 mpeg video decoding .................................................................................................... 13 3.10 audio processing ......................................................................................................... .. 14 3.11 soft modem ............................................................................................................... .... 14 3.12 video .................................................................................................................... .......... 14 contacting cirrus logic support for a complete listing of direct sales, distributor, and sales representative contacts, visit the cirrus logic web site at: http://www.cirrus.com/corporate/contacts/ preliminary product information describes products which are in production, but for which full characterization data is not yet available. advance product infor- mation describes products which are in development and subject to development changes. cirrus logic, inc. has made best effort s to ensure that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provi d ed as is without warranty of any kind (express or implied). no responsibility is assumed by cirrus logic, inc. for the use of this information, nor for inf ringements of patents or other rights of third parties. this document is the property of cirrus logic, inc. and implies no license under patents, copyrights, tradem arks, or trade secrets. no part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, 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CS98000 ds525pp1 3 4. memory map ................................................................................................................ ....... 15 4.1 processor memory map .................................................................................................. 15 4.2 host port memory map .................................................................................................... 15 4.3 internal io space map ..................................................................................................... 15 5. register description .................................................................................................... 16 5.1 CS98000 register space ................................................................................................ 16 6. pin description ........................................................................................................... ...... 25 6.1 pin assignments ........................................................................................................... ... 26 6.2 miscellaneous interface pins ........................................................................................... 31 6.3 sdram interface ........................................................................................................... .. 31 6.4 rom/nvram interface ................................................................................................... 31 6.5 video output interface .................................................................................................... .33 6.6 video input interface ..................................................................................................... .. 33 6.7 audio output/input interface ............................................................................................ 34 6.8 ac97/codec interface ................................................................................................... 34 6.9 host master/atapi interface ........................................................................................... 35 6.10 dvd i/o channel interface ............................................................................................ 35 6.11 general purpose input/output (gpio) .......................................................................... 35 6.12 power and ground ........................................................................................................ 3 5 7. package specifications ............................................................................................... 38 list of tables atapi transaction ............................................................................................................. ................ 4 CS98000 with video encoder .................................................................................................... ..... 7 absolute maximum rating ....................................................................................................... ........ 8 electrical characteristics .................................................................................................... ............ 8 table 1. host port memory map .................................................................................................. .15 table 2. internal io space map................................................................................................. .... 15 table 3. CS98000 register map and blocks ................................................................................ 16 table 4. CS98000 registers ..................................................................................................... .... 16 table 5. pin type legend ....................................................................................................... ....... 25 table 6. pin assignments....................................................................................................... ....... 26 table 7. miscellaneous interface pins .......................................................................................... 31 table 8. sdram interface ....................................................................................................... ..... 32 table 9. rom/nvram interface................................................................................................... 32 table 10. video output interface ............................................................................................... ... 33 table 11. video input interface ................................................................................................ ..... 33 table 12. audio output interface ............................................................................................... ... 34 table 13. ac97/codec interface ................................................................................................ 3 4 table 14. host master interface................................................................................................ .... 35 table 15. dvd i/o channel interface ........................................................................................... 3 6 table 16. general purpose i/o interface ...................................................................................... 36 table 17. power and ground .................................................................................................... ... 37 list of figures atapi transactions - read and write ........................................................................................... 4 sdram refresh transaction ..................................................................................................... .... 5 sdram burst write transaction ................................................................................................. ... 5 sdram burst read transaction .................................................................................................. .5 sdram timing .................................................................................................................. ............ 6 CS98000 interface with video encoder ......................................................................................... 7 CS98000 typical application ................................................................................................... ...... 9 CS98000 block diagram ......................................................................................................... ..... 10
CS98000 4 ds525pp1 1. characteristics and specifications 1.1 ac electrical specifications 1.1.1 atapi interface CS98000 can interface with atapi-type slave loader gluelessly. figure 1 illustrates a read atapi trans- action and a write atapi transaction. pio mode 4 is implemented for sufficient data transfer rate between atapi device and CS98000. atapi transaction symbol description min typ max unit tasu address valid to h_rd 25 30 - ns tdsu read data setup time 20 30 - ns tc transaction cycle time 70 75 - ns tw read or write pulse width 70 75 - ns trdh read data hold time 5 15 - ns twdh write data hold time 10 15 - ns ta h_rdy width - - 1250 ns trd read data valid to h_rdy valid 35 45 - ns tr h_rdy drive high to release time 5 - ns din dout tasu tdsu tasu twdh tc tw tw trdh a ddr valid h_rd h _d_[15:0] h_wr h_rdy ta trd tr figure 1. atapi transactions - read and write
CS98000 ds525pp1 5 1.1.2 sdram interface CS98000 interfaces with either sdram or sgram for high data bandwidth transfer. figure 2 shows the refresh cycle performed by CS98000. figure 3 shows a burst read (length = 8) transaction, while figure 4 shows a burst write (length = 8) transaction. figure 5 and the following table show detailed timing. in both figure 3 and 4, cas latency is programmed to 3. figure 2. sdram refresh transaction m_cke m_a_[11:0] m_bs_l m_ras_l m_cas_l m_we_l md[31:0] m_dqm_[3:0] m_ap figure 3. sdram burst write transaction d0 d1 d2 d3 d4 d5 d6 d7 c1 c2 c3 c4 c5 c6 c7 c0 r0 m_cko m_a_[11:0] m_bs_l m_ras_l m_cas_l m_we_l m_d_[31:0] m_dqm_[3:0] m_ap figure 4. sdram burst read transaction d0 d1 d2 d3 d4 d5 d6 d7 c1 c2 c3 c4 c5 c6 c7 c0 r0 m_cko m_a_[11:0] m_bs_l m_ras_l m_cas_l m_we_l m_d_[31:0] m_dqm_[3:0] m_ap
CS98000 6 ds525pp1 symbol description min typ max unit tmsur input to clock setup 3 ns tmhr input to clock hold 0 ns tmco clock to out 9 ns tcch clk high time 4.5 ns tccl clk low time 4.5 ns tmper clk period 10 12.2 ns tmhw output hold time 3 ns tmdow clk to data bus valid 5 ns tmsuw data valid to clk 3 ns mras,mcas mwe,ap,dqm0-3 mcke,ma-011 t ccl t cch t mper t mco dq0-dq31(write) dq0-dq31(read) clock t msur t mhr t mhw t msuw t mdow figure 5. sdram timing
CS98000 ds525pp1 7 1.1.3 video interface figure 6 illustrates the CS98000 interfaces with standard video encoder. CS98000 with video encoder symbol description min typ max unit tdsu video data setup time 5 ns tdh video data hold time 5 ns tsysu hsync or vsync to clock setup time 5 ns tsyh clock to hsync or vsync hold time 5 ns tckl video clock low time 14.8 22.2 ns tckh video clock high time 14.8 22.2 ns tsysu tdh tdsu clk27_o vdat_[7:0] h sync, vsync tckl tckh tsyh figure 6. CS98000 interface with video encoder
CS98000 8 ds525pp1 1.2 dc electrical specification absolute maximum rating electrical characteristics (ta = 0 to 70 o c) symbol description min max unit vdd io power supply voltage on i/o ring -0,5 4.6 volts vdd core power supply voltage on core logic and pll -0.5 3.6 volts v i digital input applied voltage (power applied) -0.5 5.5 volts i i digital input forced current -10 10 ma i o digital output forced current -50 50 ma t sol lead soldering temperature - 260 o c t vsol vapor phase soldering temperature - 220 o c t stor storage temperature (no power applied) -40 125 o c t amb ambient temperature (power applied) 0 70 o c p io power consumption on i/o ring (c l = 35 pf) - 57 ma p core power consumption on the core logic - 620 ma p pll power consumption on the pll logic - 15 ma parameter symbol conditions min typ max units supply voltage, io v dd 3.0 3.3 3.6 volts supply voltage, core and pll v dd 2.25 2.5 2.75 volts supply current, io i dd normal operating - 45 - ma supply current, core and pll i dd normal operating - 550 - ma input voltage, high v ih 2.0 - 5.0 volts input voltage, low v il --0.8volts input current i in v in = v dd or v ss -1 - +1 m a input pull up/down resistor r i -75- k w output voltage, high v oh @ buffer rating 2.4 - - volts output voltage, low v ol @ buffer rating - - 0.4 volts tristate leakage i oz v out = v ss or v dd -10 - +10 m a input capacitance c in -3-pf output capacitance c out -3-6- pf bidirect capacitance c bid -3-6- pf
CS98000 ds525pp1 9 2. typical application the figure 7 shows a typical example of a complete internet-dvd solution using the CS98000. CS98000 flash .5-2mb sdram 4-8mb remote keyboard/ control video encoder codec composite video phone ir s-video audio-l(3) audio-r(3) parallel port daa (3)audio dacs power reg. line power switch s/pdif flash 2mb sdram 8mb audio adc video decoder driver front panel video audio-l audio-r dvd loader (i/o chan) or atapi loader + hard drive* * hard drive useable with atapi loader figure 7. CS98000 typical application
CS98000 10 ds525pp1 3. functional description 3.1 block diagram the CS98000 block is shown in figure 8. 3.2 CS98000 device details 3.2.1 risc-32 ? powerful 32-bit risc processor ? virtual memory support ? optimizing c compiler and source level debug- ger ? big or little endian data formats support ? mac multiply/accumulate in 2 cycles with c support. ? 4 kbyte instruction cache, 2 kbyte data cache. ? single cycle instructions, runs at 81 mhz. 3.2.2 dsp-32 ? powerful 24/32 bit dsp processor ? 24 bit fixed point logic, with 54 bit accumula- tor. ? single-cycle throughput, 2 cycle latency multi- ply accumulate, 32 bit simple integer logic. 8 kbyte instruction cache, 8 kbyte program visible local memory ? single cycle instructions, runs at 81 mhz. 3.2.3 system controls ? include several hardware lockable semaphore registers ? general-purpose register for inter-processor communication ? 32-bit timers for i/o and other uses, with pro- grammable interval rates risc-1 instruction cache data cache mmu mac risc-2 instruction cache data cache mmu mac mpeg decoder vlc parser idct ram motion comp system sync stc interrupts external interface serial interface programmable i/o infrared input dvd atapi / lbus interface memory controller sdram control flash control dataflow engine dma / bitblit sram buffer system controls registers pll dsp instruction cache x,y data memory cpu / mac audio interface pcm out pcm in spdif out subpicture decoder decoder scaler video processor on-screen display picture-in-picture video / graphics display video input filter scaler figure 8. CS98000 block diagram
CS98000 ds525pp1 11 ? both hardware and software interrupts on data or debug ? performance monitors which measures dram bandwidth, usage, and rsk performance ? built in plls generate all required clocks from 27 mhz input clock. 3.2.4 memory controller ? supports sdram, and sgram, from 2 mb to 32 mb. ? supports multiple banks of flash and rom up to 32 mb. ? 32-bit data bus for dram, 8 or 16 bit data bus for rom. 3.2.5 data flow engine ? 2432 bytes of internal memory. ? dma to/from main ram into local sram. ? supports endian conversion and byte, short, long data formats on dma. ? supports block transfers for graphics bit blits. 3.2.6 mpeg video decoder ? supports vcd, vcd 3.0, svcd, dvd video standards. ? supports trick features, including smooth 2x play and reverse play. ? special anti-tearing logic controls picture de- code and presentation. ? advanced error concealment hardware. 3.2.7 system synchronization ? system time clock (stc) for audio/video syn- chronization ? flexible interrupt structure for controlling de- code and presentation times ? hardware scheduling of subpicture and high- light events 3.2.8 audio interface ? supports pcm, i 2 s and iec-958 outputs at up to 96 khz output rate. ? 8 output channels, 2 input channels. 3.2.9 video input ? ntsc/pal video decoder input interface. ? built in variable down scaling, handles ccir 601 to qcif input formats. ? video input image can be displayed in small window, or as main picture 3.2.10 external interface ? serial i2c master and slave port. ? 29 independent fully programmable bi-direc- tional i/o pins. ? 8 edge or level detection interrupt pins. ? hardware assisted support for infrared remote devices, such as remote control, infrared key- board, mouse, printer, and more. ? programmable parallel host master and slave interface supports many formats including atapi, isa, and more. ? io channel interface supports standard dvd loader protocols ? serial interface supports ac-97 and other stan- dard modem codec protocols 3.2.11 video processor ? supports 24 bit 4:2:0 and 4:2:2 video modes, and 16 bit true color graphics modes.on screen display module supports 2-bit, 4-bit, or 8-bit pixel modes. it supports 3 separate regions and 16 transparency overlay levels ? picture-in-picture module includes horizontal and vertical downscaling. supports program- mable output sizes, positions, and borders ? overlay mixer with rgb to yuv conversion and output formatting
CS98000 12 ds525pp1 ? supports 4:2:0, 4:2:2, yuv655, rgb565 and rgb555 frame buffer inputs. ? high quality scaling using a vertical and a hor- izontal 16 taps polyphase programmable filter, to support any size image up to 768x576. ? programmable sharpening and de-blocking fil- ters. ? 5 taps programmable adaptative anti-flicker fil- tering for graphics source. ? master or slave video sync configuration. ? outputs 4:2:2 video in ccir-601 or ccir-656 format. ? multiple video plains overlay (main video/vid- eo input/picture_in_picture picture/on_screen display/cursor). ? gamma correction. 3.2.12 sub-picture processor ? run-length decode dvd sub-pictures and svcd ogt formats ? hardware vertical scaling supports ntsc-pal format conversion ? 16 level alpha blending ? provides hardware cursor mode for non-dvd applications 3.2.13 system functions ? 128 and 208-pin pqfp packages. ? all i/o pins are 3 v with 5 v tolerance. ? advanced 0.25 micron cmos technology. ? internal processors run at 81 mhz ? supports low power modes and clock shutoff. 3.3 risc processor the CS98000 includes two powerful, proprietary 32-bit risc processors, called risc, with optimiz- ing c compiler support and source level debugger. the risc has an instruction set that is a superset of mips r3000. in addition to the standard mips r3000 instruction code, the risc processor also has a mac engine, which performs multiply/accu- mulate in 2 cycles in a pipelined fashion with c support, effectively achieving single cycle throughout. there are other instructions that are de- signed to help with performing mpeg1/2 decod- ing. the CS98000 fully supports many real time operating systems (rtos) such as windriver ? os and ati. the risc processor co-ordinates on- chip multi-threaded tasks, as well as system activi- ties such as remote control and front panel control. 3.4 dsp processor the CS98000 contains a proprietary digital signal processor (dsp) called dsp, which is optimized for audio and sound applications. the dsp per- forms 32 bit simple integer operations, and has a 24 bit fixed point logic unit, with a 54 bit accumulator. there are 32 general-purpose registers, and eight independent address generation registers, featur- ing: post-increment alu, linear and circular buffer operations, bit reverse alu operations, and dual operand read from memory. the multiply-accumu- lator has single-cycle throughput, with two cycle latency. the dsp is optimized for bit packing and unpacking operations. the interface to main mem- ory is designed for handling flexible block sizes and skip counts. 3.5 memory control the dram interface performs the sdram con- trol and arbitration functions for all the other mod- ules in the CS98000. the dram interface services and arbitrates a number of clients and stores their code and/or data within the local memory. this ar- bitration and scheduling guarantees the allocation of sufficient bandwidth to the various clients. the dram interface supports up to 32 mb. for a typ- ical dvd player application, CS98000 requires 4 mb memory space.
CS98000 ds525pp1 13 sharing the same interface, CS98000 also supports flash rom, otp, or mask rom interface. code is stored in rom. after system is booted, the code is shadowed inside dram for execution. the flash rom interface is provided so that the code can be upgraded in the field once the communications channel is established (modem port, cd-r, serial port. utility software will be provided to debug and upgrade code for the system manufacturer. 3.6 dataflow control (dma) the dma controller moves data between the exter- nal memory and an internal memory. the external memory address can be specified using a register, or in fifo mode, using start and end address regis- ters. separate start/end address registers are used for dma read and write operations. the dma in- terface also has a block transfer function, which al- lows for the transfer of one block of data from one external memory location to another external mem- ory location. in effect, combining a dma read and write into one operation. in addition, the dma write operation allows for byte, short, word, and other types of masking. 3.7 system control functions the system control functions are used to coordinate the activities of the multiple processors, and to pro- vide the supporting system operations. four 32-bit communication registers are available inter-pro- cessor communication, and eight semaphore regis- ters are used for resource locking. timers are available for general-purpose functions, as well as more specialized functions such as watchdog tim- ers and performance monitoring. the large number of general purpose i/os offers flexibility in system configurations. an i2c master allows for control of other i2c devices, such as a video encoder. an i2c slave port shares the same pins, and can be used for debug functions. interrupts can be generated on specific or generic events. infrared inputs can be filtered of glitches or stored unfiltered into memo- ry. control of all the internal clocks is also possi- ble. internal plls are used to generate the internal system and memory clocks, and audio clocks of any widely used frequency. 3.8 dvd/atapi interface the CS98000 has a programmable interface port which can be configured to connect to industry standard cd/dvd loaders without external glue logic. the cd/dvd interface fully supports popu- lar cd/dvd loaders such as sanyo, sony and avs. the interface consists of dvd control and data ports, and an optional cd control/data port. the CS98000 hardware manages the dvd inter- face and moving data to an arbitrary size input fifo in dram. the same interface pins can be optionally config- ured as a generic 16-bit host master port. in this mode, the CS98000 can control up to four devices (using 4 chip select outputs), each of which may use different protocol and timing. the interface can be set up in atapi mode, to connect directly to any atapi dvd loader (using two chip selects). si- multaneously, the other two chip selects can be configured to connect to other devices, such as a super i/o chip or hard disk. a third option is to configure the interface for mi- cro-less dvd loader operation, which may also be configured to connect without external glue logic. 3.9 mpeg video decoding compressed mpeg data is read from the dvd disk into an input fifo in dram. the data flow (dma) controller moves video packets from the input fifo into the mpeg decoders input fifo (also in dram). the dma controller can also per- form advanced functions such as start code search, relieving the risc processors. the system sync function is used to control the timing of mpeg pic- ture decoding. the mpeg video decoder process- es i, b and p frames, and writes to video frame buffers in dram for output to the display. special
CS98000 14 ds525pp1 anti-tearing logic ensures that currently displayed frame buffers are not overwritten. 3.10 audio processing compressed audio data is read from the dvd disk into an input fifo in dram. the data is decom- pressed, then written to a pcm output fifo, also in dram. presentation time stamps (pts) are ex- tracted from the stream to update the stc, in order to maintain audio/video synchronization. the dma and decompression stages of audio pro- cessing can be done with a combination of the dma unit, dsp and risc processors. the dsp is optimized for audio processing, so most common formats can be handled by the dsp alone, includ- ing ac-3, mpeg2 audio, and mp3. the dsp has enough reserve bandwidth to handle the karaoke echo-mix and pith shift, and ac-3 down-mix func- tions. the audio output data is written into a dram fifo in 16, 18 or 20 bit pcm format. a flexible au- dio output stage can simultaneously output 8 chan- nels of pcm data to audio dacs, or 6 channels of audio data plus an iec-958 encoded output, at up to 96 khz. the audio interface also includes a flex- ible pcm input interface, which can input a wide range of protocols from an audio adc or iec-958 receiver. 3.11 soft modem the soft modem processing is handled by one of the risc processors, which is typically dedicated for that function. data rates up to 56 k (v.90 pro- tocol) are supported. the CS98000 interfaces to a simple external codec/daa circuit using a flex- ible serial interface. the serial interface is a fully programmable, bi-directional interface and can be used either as a pcm interface or as an ac97 inter- face. in pcm mode, the sample size could be ad- justed to 20, 18 or 16 bits to match common dac and adc formats, or any other specific size. in ac97 mode, any slot can be used to interface either a modem codec or an audio codec. 3.12 video the digital video interface provides flexible and powerful means of outputting digital video data to external devices in ccir601/3 and ccir656 yuv formats. the interface directly supports ntsc/pal video encoder, in both master and slave sync configurations. the internal frame buff- er format could be 4:2:0, 4:2:2, yuv655, rgb565 and rgb555. cirrus logic provides some easy to use utilities in order to get the best advantage of the powerful video filtering capabilities of the CS98000. the CS98000 also features an ntsc/pal video decoder input interface. the in- terface accepts ccir, cif, and qcif formats, out of many tv decoders on the market. the video processor also allows multiple video plans overlay (main video / video input / picture_in_picture / on_screen display / cursor). CS98000 has been proven to work with many tv encoders on the market with brands, such as, crystal, brooktree, adi, and avs. the video input scaler (vis) module inputs 8-bit digital video data from a camera or pal/ntsc de- coder, optionally down-scales to sif or qsif, and stores the data in one to three dram frame buff- ers. the scaled image, with a border, can be over- layed anywhere on the screen into a ? or ?-screen sized window by the picture in picture (pip) mod- ule. an alternate method of using the video input func- tion is to input a full sized picture, and present it on the screen full size (bypass mode). in this mode, the pip module can place full motion dvd images in the small window. an internal glitch-free mux can switch the video processor clock source from the internal clock to the video input clock, allowing the pip mode to switch back and forth on the fly, with no dropout.
CS98000 ds525pp1 15 4. memory map 4.1 processor memory map the CS98000 externally supports up to 32 mbytes dram and 16 mbytes rom/nvram. table lists the memory map as viewed by the risc proces- sors, and identifies whether each segment is mapped or cacheable. 4.2 host port memory map table 1 lists the memory map as viewed by host slave port. 4.3 internal io space map table 2 shows how the internal io space is mapped between general registers, internal sram ports, and the risc processors debug port. processor byte address description cacheable 0000_0000 C 07ff_ffff dram (mapped) y 8000_0000 - 81ff_ffff dram (32 mbytes) y 9400_0000 C 9cff_ffff 16 bit nvram write (16 mbytes) n 9c00_0000 C 9cff_ffff 16 bit nvram/rom (16 mbytes) y 9d00_0000 C 9dff_ffff 8 bit nvram/rom (16 mbytes) y a000_0000 C a1ff_ffff dram (32 mbytes) n b000_0000 C b003_ffff internal i/o (256 kbytes) n b400_0000 C bcff_ffff 16 bit nvram write (16 mbytes) n bc00_0000 C bcff_ffff 16 bit nvram/rom (16 mbytes) n bd00_0000 C bdff_ffff 8 bit nvram/rom (16 mbytes) n c000_0000 C ffff_ffff dram (mapped) y memory map - risc processor host byte address description 0000 0000 C 003f ffff internal i/o space 1000 0000 C 13ff ffff dram space (16 mbytes) 1400 0000 C 17ff ffff nvram space (16 mbytes) table 1. host port memory map byte address offset description 0_0000 C 0_2fff general registers 0_3000 C 1_ffff general internal sram 2_0000 C 2_ffff risc_0 internal sram/registers 3_0000 C 3_ffff risc_1 internal sram/registers table 2. internal io space map
CS98000 16 ds525pp1 5. register description 5.1 CS98000 register space table 3 lists the register groups, and how they are split among the main CS98000 functional blocks. table 4 lists all the registers for the CS98000 and their addresses, and indicates whether the registers are read/write (r/w), read only (ro) or write only (wo). CS98000 register block 000xx, 010xx general 001xx host 002xx drc 003xx dma 004xx dvd interface 005xx serial interface 006xx dsp 007xx sync control 008xx mpeg video decoder 009xx video input scaler 00axx picture-in-picture 00bxx video processor 00cxx subpicture display 00dxx on-screen display 00exx pcm in/out 02xxxx risc_0 03xxxx risc_1 table 3. CS98000 register map and blocks address type function register name 000 r/w general command 010 r/w general interproc_comm_register_0 014 r/w general interproc_comm_register_1 018 r/w general interproc_comm_register_2 10c r/w general interproc_comm_register_3 020 r/w general semiphore_register_0 024 r/w general semiphore_register_1 028 r/w general semiphore_register_2 02c r/w general semiphore_register_3 030 r/w general semiphore_register_4 034 r/w general semiphore_register_5 038 r/w general semiphore_register_6 table 4. CS98000 registers
CS98000 ds525pp1 17 03c r/w general semiphore_register_7 040 ro general genio_read_data 044 r/w general genio_write_data 048 r/w general genio_tri_state_enable 04c r/w general genio_positive_edge 050 r/w general genio_negative_edge 054 r/w general genio_interrupt_status 058 r/w general genio_positive_edge_mask 05c r/w general genio_negative_edge_mask 060 r/w general genio_level_mask 064 r/w general genio_mode register 1040 ro general geniomis_read_data 1044 r/w general geniomis_write_data 1048 r/w general geniomis_tri_state_enable 104c r/w general geniomis_positive_edge 1050 r/w general geniomis_negative_edge 1054 r/w general geniomis_interrupt_status 1058 r/w general geniomis_positive_edge_mask 105c r/w general geniomis_negative_edge_mask 1060 r/w general geniomis_level_mask 1064 r/w general geniomis_mode register 1068 ro general geniodvd_read_data 106c r/w general geniodvd_write_data 1070 r/w general geniodvd_tri_state_enable 1074 ro general geniohst_read_data 1078 r/w general geniohst_write_data 107c r/w general geniohst_tri_state_enable 068 r/w general i2c_mstr_read_comand 06c r/w general i2c_mstr_write_1byte 070 r/w general i2c_mstr_write_2bytes 074 r/w general i2c_mstr_control 078 ro general i2c_mstr_status 07c ro general i2c_mstr_read_data 080 r/w general rsk0_interrupt_mask 084 wo general rsk0_interrupt_set 088 r/w general rsk0_interrupt_status 08c ro general rsk0_interrupt_cause 090 r/w general dsp_interrupt_mask 094 wo general dsp_interrupt_set 098 r/w general dsp_interrupt_status 09c ro general dsp_interrupt_cause table 4. CS98000 registers (continued)
CS98000 18 ds525pp1 0a0 r/w general rsk0_interrupt_mask2 0a4 wo general rsk0_interrupt_set2 0a8 r/w general rsk0_interrupt2_status 0ac ro general rsk0_interrupt_cause2 1080 r/w general rsk1_interrupt_mask 1084 wo general rsk1_interrupt_set 1088 r/w general rsk1_interrupt_status 108c ro general rsk1_interrupt_cause 10a0 r/w general rsk1_interrupt_mask2 10a4 wo general rsk1_interrupt_set2 10a8 r/w general rsk1_interrupt2_status 10ac ro general rsk1_interrupt_cause2 0b0 r/w general dsp_interrupt_mask2 0b4 wo general dsp_interrupt_set2 0b8 r/w general dsp_interrupt2_status 0bc ro general dsp_interrupt_cause2 0c0 r/w general timer_0 0c4 r/w general timer_1 0c8 r/w general timer_2 0cc r/w general timer_3 0d0 r/w general timer_control 0d4 ro general performance_monitor_count 0d8 r/w general timer_m_over_n 0e0 r/w general ir_control 0e4 r/w general ir_dram_start_address 0e8 r/w general ir_dram_end_address 0ec ro general ir_dram_write_address 0f0 r/w general pll_control_register1 10f0 r/w general low_power_clock_control 0f4 r/w general pll_control_register2 10f4 r/w general pll_control_register3 0f8 r/w general pll_turn_off 0fc r/w general pll_clock_divider 100 r/w host device_1_control 104 r/w host device_2_control 108 r/w host device_3_control 10c r/w host device_4_control 110 r/w host write_data_port 114 ro host read_data_port 120 r/w host host_start_address 124 r/w host dram start address table 4. CS98000 registers (continued)
CS98000 ds525pp1 19 128 r/w host stream_transfer_size 12c r/w host dram_burst_threshold 13c r/w host host_master_control 200 r/w dram controller dram_controller_priority0 204 r/w dram controller dram_controller_priority1 208 r/w dram controller dram_controller_priority2 20c r/w dram controller dram_controller_priority3 210 r/w dram controller dram_controller_priority4 214 r/w dram controller dram_controller_setup 218 r/w dram controller dram_command 21c r/w dram controller dram_controller_mb_width 220 r/w dram controller dram_controller_debug_control 224 ro dram controller dram_debug_status 300 wo dma dma_enable 304 r/w dma dma_control 308 ro dma dma_status 30c r/w dma xfer_byte_cnt 310 r/w dma dram_byte_start_addr 314 r/w dma sram_byte_start_addr 318 r/w dma fifo_start_rd_addr 31c r/w dma fifo_start_wr_addr 328 r/w dma search_control 32c ro dma search_status 330 r/w dma fifo_end_rd_addr 334 r/w dma fifo_end_wr_addr 338 r/w dma lines_and_skip 33c r/w dma byte_mask_pattern 400 r/w cd/dvd dvd1 _control 404 r/w cd/dvd dvd1 _fifo_base_address 408 r/w cd/dvd dvd1_fifo_size 40c r/w cd/dvd dvd1_sector 410 ro cd/dvd dvd1_start_of_sector 414 ro cd/dvd dvd1_current_dram_address 418 r/w cd/dvd cd_control 41c r/w cd/dvd cd_error_status 438 ro cd/dvd dvd1_status 440 r/w ser/dci dci_control_reg 444 ro ser/dci dci_status 448 r/w ser/dci dci_dram_rd_start_addr 44c r/w ser/dci dci_dram_wr_start_addr 450 r/w ser/dci dci_nbytes_sent table 4. CS98000 registers (continued)
CS98000 20 ds525pp1 454 r/w ser/dci dci_mbytes_switch 458 ro ser/dci dci_diagnostic 45c r/w ser/dci dci_active 540 r/w ser/dci serial_frame_sync_control 544 r/w ser/dci serial_output_input_control 548 r/w ser/dci ac97_codec_control 54c r/w ser/dci ac97_codec_command 550 r/w ser/dci serial_output_fifo_start_address 554 r/w ser/dci serial_output_fifo_end_address 558 r/w ser/dci serial_input_fifo_start_address 55c r/w ser/dci serial_input_fifo_end_address 560 ro ser/dci serial_output_fifo_read_address 564 ro ser/dci serial_input_fifo_write_address 568 r/w ser/dci serial_clock_synthesis_parameters 56c ro ser/dci codec_register_status 570 r/w ser/dci slot5_register_data 574 r/w ser/dci slot10_register_data 578 r/w ser/dci slot11_register_data 57c r/w ser/dci slot12_register_data 580 r/w ser/dci out_fifo_int 584 r/w ser/dci in_fifo_int 588 r/w ser/dci rate_control 600 wo dsp dsp_boot_code_start_address 604 wo dsp dsp_run_enable 6xx ro dsp dsp_program_cntrun_status 700 r/w sync control audio_sync_control 704 r/w sync control video_sync_control 708 ro sync control video_sync_status 70c r/w sync control wait_line 710 r/w sync control frame_period 714 r/w sync control stc_interval 718 r/w sync control system_time_clock 71c r/w sync control top_bits 720 r/w sync control video_pts_fifo_start_address 724 r/w sync control video_pts_fifo_end_address 728 r/w sync control video_pts_fifo_write_address 72c ro sync control video_pts_fifo_read_address 730 r/w sync control subpicture_pts_fifo_start_address 734 r/w sync control subpicture_pts_fifo_end_address 738 r/w sync control subpicture_pts_fifo_write_address 73c ro sync control subpicture_pts_fifo_read_address table 4. CS98000 registers (continued)
CS98000 ds525pp1 21 740 r/w sync control highlight_start_pts 744 r/w sync control highlight_end_pts 748 r/w sync control button_end_pts 74c rw sync control highlight_control_information_address 750 r/w sync control video_pts 754 r/w sync control audio_pts 758 ro sync control subpicture_pts 75c ro sync control audio_time 760 ro sync control video_sync_debug 764 r/w sync control sp_drc_vpts_debug 768 r/w sync control frame_count_interrupt 76c r/w sync control video_dts 770 ro sync control sync_interrupt_status 774 r/w sync control sync_interrupt_control 778 wo sync control sync_interrupt_set 77c wo sync control sync_interrupt_clear 800 r/w mpeg vid. decoder mpeg_video_control 804 r/w mpeg vid. decoder mpeg_video_setup 808 r/w mpeg vid. decoder mpeg_video_fifo_start_address 80c r/w mpeg vid. decoder mpeg_video_fifo_end_address 810 ro mpeg vid. decoder mpeg_video_fifo_current_address 814 ro mpeg vid. decoder mpeg_video_horiz_pan_vector 818 wo mpeg vid. decoder mpeg_video_fifo_add_bytes 81c ro mpeg vid. decoder mpeg_video_fifo_curr_bytes 820 r/w mpeg vid. decoder mpeg_video_fifo_interrupt_bytes 824 ro mpeg vid. decoder mpeg_video_fifo_total_bytes 828 ro mpeg vid. decoder mpeg_video_status 82c r/w mpeg vid. decoder macroblock width_height 830 ro mpeg vid. decoder mpeg_video_debug 834 r/w mpeg vid. decoder mpeg_u_offset 83c r/w mpeg vid decoder mpeg_i_base_register 840 r/w mpeg vid decoder mpeg_p_base_register 844 r/w mpeg vid decoder mpeg_dest_control 848 ro mpeg vid decoder mpeg_software_flags 84c r/w mpeg vid decoder mpeg_v_offset 854 r/w mpeg vid decoder mpeg_antitearwindow 858 r/w mpeg vid decoder mpeg_error_pos 900 r/w vis vis_control 904 r/w vis vis_startx 908 r/w vis vis_endx 90c r/w vis vis_starty table 4. CS98000 registers (continued)
CS98000 22 ds525pp1 910 r/w vis vis_endy 914 r/w vis vis_frame_base 918 r/w vis vis_u_offset 91c r/w vis vis_v_offset 920 r/w vis vis_frame_size a00 r/w pip pip_control a04 r/w pip pip_vidbrdstartx a08 r/w pip pip_vidbrdendx a0c r/w pip pip_vidbrdstarty a10 r/w pip pip_vidbrdendy a14 r/w pip pip_borderclr a18 r/w pip pip_vscale a1c r/w pip pip_line_offnum_bot a20 r/w pip pip_frbasey a24 r/w pip pip_frbaseu a28 r/w pip pip_frbasev a2c r/w pip pip_line_width a30 r/w pip pip_ line_offnum_top a34 r/w pip pip_frame_size b00 r/w video processor video_processor_control b04 r/w video processor video_dram_line_length b08 r/w video processor display_activex b0c r/w video processor display_activey b10 r/w video processor blank_color b14 r/w video processor internal_hsync_count b18 r/w video processor internal_vsync_count b1c r/w video processor horizontal_y_offset b20 r/w video processor horizontal_uv_offset b24 r/w video processor vertical_offset b28 r/w video processor video_line_size b2c r/w video processor frame_buffer_base b30 r/w video processor video_line_mode_buffer b34 r/w video processor horizontal_vertical_filter b38 r/w video processor source_x_offset b3c r/w video processor horizontal_video_scaling b40 r/w video processor frame_v_buffer_compressed_offset b44 wo video processor mb_width b48 wo video processor anti-flicker b4c wo video processor anti-flicker b50 wo video processor anti-flicker b54 wo video processor anti-flicker table 4. CS98000 registers (continued)
CS98000 ds525pp1 23 b58 wo video processor anti-flicker b5c wo video processor gamma control b60 wo video processor gamma control b64 wo video processor gamma control b68 wo video processor gamma control b6c wo video processor gamma control b70 wo video processor gamma control b74 wo video processor gamma control b78 wo video processor gamma control b7c r/w video processor vid_sync adjust c00 r/w subpicture subpicture_color0 c04 r/w subpicture subpicture_color1 c08 r/w subpicture subpicture_color2 c0c r/w subpicture subpicture_color3 c10 r/w subpicture subpicture_color4 c14 r/w subpicture subpicture_color5 c18 r/w subpicture subpicture_color6 c1c r/w subpicture subpicture_color7 c20 r/w subpicture subpicture_color8 c24 r/w subpicture subpicture_color9 c28 r/w subpicture subpicture_color10 c2c r/w subpicture subpicture_color11 c30 r/w subpicture subpicture_color12 c34 r/w subpicture subpicture_color13 c38 r/w subpicture subpicture_color14 c3c r/w subpicture subpicture_color15 c40 r/w subpicture subpicture_dci_address c44 r/w subpicture subpicture_hli_address c50 r/w subpicture subpicture_control c54 r/w subpicture subpicture_display_offset c58 r/w subpicture subpicture_display_scale d00 ro on screen display osd_status d04 r/w on screen display osd_control d08 r/w on screen display osd_color_number d0c r/w on screen display osd_color_data d10 r/w on screen display osd_region1_control d14 r/w on screen display osd_region1_hlimits d18 r/w on screen display osd_region1_vlimits d1c r/w on screen display osd_region1_drambase d20 r/w on screen display osd_region2_control d24 r/w on screen display osd_region2_hlimits table 4. CS98000 registers (continued)
CS98000 24 ds525pp1 d28 r/w on screen display osd_region2_vlimits d2c r/w on screen display osd_region2_drambase d30 r/w on screen display osd_region3_control d34 r/w on screen display osd_region3_hlimits d38 r/w on screen display osd_region3_vlimits d3c r/w on screen display osd_region3_drambase d40 r/w on screen display osd_blend d44 r/w on screen display osd_debug1 d48 r/w on screen display osd_debug2 e00 r/w pcm pcm_run_clear e04 r/w pcm pcm_output_control e08 r/w pcm pcm_out_fifo_start_address e0c r/w pcm pcm_out_fifo_end_address e10 r/w pcm pcm_out_fifo_interrupt_address e14 ro pcm pcm_out_fifo_current_address e18 r/w pcm spdif_channel_status e20 r/w pcm pcm_input_control e24 r/w pcm pcm_in_fifo_start_address e28 r/w pcm pcm_in_fifo_end_address e2c r/w pcm pcm_in_fifo_interrupt_address e30 r/w pcm pcm_out_fifo_interrupt_address2 e34 r/w pcm pcm_out_fifo_interrupt_address3 e38 ro pcm pcm_in_fifo_current_address e3c rw pcm spdif_output_control e40 rw pcm spdif_output_fifo_start_address e44 rw pcm spdif_output _fifo_end_address e48 ro pcm spdif_output _fifo_current_address e4c rw pcm spdif_output _fifo_interrupt_address e50 rw pcm spdif_output_add_block 2xxxx r/w rsk0 risc 0 processor registers 3xxxx r/w rsk1 risc 1 processor registers table 4. CS98000 registers (continued)
CS98000 ds525pp1 25 6. pin description table 5 lists the conventions used to identify the pin type and direction in the table that follows. i input is input, with schmitt trigger id input, with pull down resistor iu input, with pull up resistor o output o4 output C 4ma drive o8 output C 8ma drive t4 tri-state-able output C 4ma drive b bi-direction b4 bi-direction C 4ma drive b4u bi-direction C 4ma drive, with pull-up b8u bi-direction C 8ma drive, with pull-up b4s bi-direction C 4ma drive, with schmitt trigger b4su bi-direction C 4ma drive, with pull-up and schmitt trigger pwr +2.5v or +3.3v power supply voltage gnd power supply ground name_n low active name_l low active table 5. pin type legend h_d_[15:0] h_cs_[3:0] h_a_[4:0] h_ale h_rd h_wr h_cko h_rdy vin_d[7:0] vin_hsnc vin_vsnc vin_clk vin_fld m_a_[11:0] m_bs_l m_d_[31:0] m_dqm_[3:0] m_ras_l m_cas_l m_we_l m_ap m_cke m_cko nvr_oe_l nvr_wr_l hsync vsync clk27_o vdat_[7:0] aud_bck aud_lrck aud_do_[3:0] ain_bck ain_lrck ain_data cdc_di cdc_do cdc_rst cdc_ck cdc_sy gpio_d[20-0] ir_in mfg_tst xtlclock rst_n CS98000 host/loader (30) video in (12) memory if (57) video out (11) dac out (7) misc. (41) codec if (5) adc in (3) spdif_o gpio_h[16-14] gpio_v10 gpio_[15-10, 8-7, 4-2, 0]
CS98000 26 ds525pp1 6.1 pin assignments table 6 lists the pin number, pin name and pin type for the 208 pin CS98000 package. the primary function and pin direction is shown for all signal pins. for some signal pins, a secondary function and direction are also shown. for pins having more than one function, the primary function is chosen when the chip is reset. pin name type primary function dir secondary function dir note 1 vdd_pll pwr pll power 2.5v 2 m_a_11 o8 sdram address[11] o rom/nvram address[11] o 3 m_a_10 o8 sdram address[10] o rom/nvram address[10] o 4 gpio_d18 b4u geniodvd[18] b system clock pll bypass i 5 m_a_9 o8 sdram address[9] o rom/nvram address[9] o 6 m_a_8 o8 sdram address[8] o rom/nvram address8] o 7 m_a_7 o8 sdram address[7] o rom/nvram address[7] o 8 gpio_d16 b4su geniodvd[16] b 9 m_a_6 o8 sdram address[6] o rom/nvram address[6] o 10 m_a_5 o8 sdram address[5] o rom/nvram address[5] o 11 m_a_4 o8 sdram address[4] o rom/nvram address[4] o 12 gpio_d17 b4u geniodvd[17] b 13 m_a_3 o8 sdram address[3] o rom/nvram address[3] o 14 m_a_2 o8 sdram address[2] o rom/nvram address[2] o 15 m_a_1 o8 sdram address[1] o rom/nvram address[1] o 16 m_a_0 o8 sdram address[0] o rom/nvram address[0] o 17 gpio_d19 b4u geniodvd[19] b memory clock pll bypass i 18 vss_io gnd i/o gr ound 19 m_cko o8 sdram clock o 20 vdd_io pwr i/o power 3.3v 21 m_bs_l o8 sdram bank select o 22 m_cke b8 sdram clock enable o geniomis(7) b 23 m_ap o8 sdram auto pre-charge o 24 m_ras_l o8 sdram row strobe o 25 m_cas_l o8 sdram column strobe o 26 gpio_d20 b4u geniodvd[20] b 27 m_we_l o8 sdram write enable o 28 m_dqm_0 o8 sdram dqm[0] o 29 m_dqm_1 o8 sdram dqm[1] o 30 gpio_d0 b4u geniodvd[0] b 31 m_dqm_2 o8 sdram dqm[2] o 32 m_dqm_3 o8 sdram dqm[3] o 33 m_d_8 b8u sdram data[8] b rom/nvram data[8] b 34 gpio_d1 b4u geniodvd[1] b 35 vss_io gnd i/o gr ound table 6. pin assignments
CS98000 ds525pp1 27 36 vss_core gnd core ground 37 m_d_7 b8u sdram data[7] b rom/nvram data[7] b 38 vdd_io pwr i/o power 3.3v 39 gpio_d2 b4u geniodvd[2] b 40 m_d_9 b8u sdram data[9] b rom/nvram data[9] b 41 vdd_core pwr core power 2.5v 42 m_d_6 b8u sdram data[6] b rom/nvram data[6] b 43 gpio_d3 b4u geniodvd[3] b 44 m_d_10 b8u sdram data[10] b rom/nvram data[10] b 45 m_d_5 b8u sdram data[5] b rom/nvram data[5] b 46 m_d_11 b8u sdram data[11] b rom/nvram data[11] b 47 gpio_d4 b4u geniodvd[4] b 48 m_d_4 b8u sdram data[4] b rom/nvram data[4] b 49 m_d_12 b8u sdram data[12] b rom/nvram data[12] b 50 gpio_d5 b4u geniodvd[5] b 51 m_d_3 b8u sdram data[3] b rom/nvram data[3] b 52 unused may leave unconnected 53 unused may leave unconnected 54 m_d_13 b8u sdram data[13] b rom/nvram data[13] b 55 m_d_2 b8u sdram data[2] b rom/nvram data[2] b 56 m_d_14 b8u sdram data[14] b rom/nvram data[14] b 57 gpio_d6 b4u geniodvd[6] b 58 vss_io gnd i/o gr ound 59 m_d_1 b8u sdram data[1] b rom/nvram data[1] b 60 m_d_15 b8u sdram data[15] b rom/nvram data[15] b 61 gpio_d7 b4u geniodvd[7] i b 62 m_d_0 b8u sdram data[0] b rom/nvram data[0] b 63 vss_core gnd core ground 64 m_d_24 b8u sdram data[24] b rom/nvram address[20] o 65 gpio_d11 b4u geniodvd[11] b 66 vdd_core pwr core power 2.5v 67 m_d_23 b8u sdram data[23] b rom/nvram address[19] o 68 m_d_25 b8u sdram data[23] b rom/nvram address[21] o 69 gpio_d10 b4u geniodvd[10] b 70 m_d_22 b8u sdram data[22] b rom/nvram address[18] o 71 m_d_26 b8u sdram data[26] b rom/nvram address[22] o 72 m_d_21 b8u sdram data[21] b rom/nvram address[17] o 73 gpio_d9 b4u geniodvd[9] b 74 m_d_27 b8u sdram data[27] b rom/nvram address[23] o 75 m_d_20 b8u sdram data[20] b rom/nvram address[16] o 76 m_d_28 b8u sdram data[28] b table 6. pin assignments (continued)
CS98000 28 ds525pp1 77 gpio_d8 b4u geniodvd[8] b 78 m_d_19 b8u sdram data[19] b rom/nvram address[15] o 79 m_d_29 b8u sdram data[29] b 80 m_d_18 b8u sdram data[18] b rom/nvram address[14] o 81 nv_we_l b4u nvram write enable o geniomis[8] b 82 vss_core gnd core ground 83 m_d_30 b8u sdram data[30] b rom/nvram decode low o 84 vdd_core pwr core power 2.5v 85 h_ale b4u host address latch o geniohst[13] b 86 m_d_17 b8u sdram data[18] b rom/nvram address[13] o 87 m_d_31 b8u sdram data[31] b rom/nvram decode high o 88 m_d_16 b8u sdram data[16] b rom/nvram address[12] o 89 gpio_h14 b4u geniohst[14] b 90 nv_oe_l o4 rom/nvram output enable o 91 vdd_io pwr i/o power 3.3v 92 h_rd b4s host read strobe o dvd data strobe i 1 93 h_wr b4 host write strobe o dvd data enable i 1 94 gpio_h15 b4u geniohst[15] b 95 h_rdy b4 host ready i dvd data ready o 1 96 vss_io gnd i/o gr ound 97 h_a_2 b4 host address[2] o geniohst[10] b 1 98 gpio_h16 b4u geniohst[16] b 99 h_a_1 b4 host address[1] o geniohst[9] b 1 100 h_a_0 b4 host address[0] o geniohst[8] b 1 101 h_cs_1 b4 host chip select [1] o dvd error i 1 102 h_a_4 b4 host address[4] o geniohst[12] b 1 103 vss_core gnd core ground 104 vss_pll gnd pll ground 105 vdd_pll pwr pll power 2.5v 106 h_cs_0 b4 host chip select[0] o dvd start sector i 1 107 h_a_3 b4 host address[3] o geniohst[11] b 1 108 vdd_core pwr core power 2.5v 109 h_d_15 b4 host data[15] b cd data i 1, 2 110 h_d_14 b4 host data[14] b cd left right clock i 1, 2 111 h_cs_3 b4 host chip select[3] o geniohst[18] b 1 112 h_d_13 b4s host data[13] b cd clock i 1, 2 113 h_d_12 b4 host data[12] b cd error i 1, 2 114 h_d_11 b4 host data[11] b dvd control data in i 1, 2 115 h_cs_2 b4 host chip select[2] o geniohst[17] b 1 116 h_d_10 b4 host data[10] b dvd control data out o 1, 2 table 6. pin assignments (continued)
CS98000 ds525pp1 29 117 h_d_9 b4 host data[9] b dvd control ready i 1, 2 118 h_d_8 b4 host data[8] b dvd control clock o 1, 2 119 vss_io gnd i/o gr ound 120 h_cko b4 host clock o geniohst[19] b 1 121 h_d_7 b4 host data[7] b dvd data[7] i 1 122 h_d_6 b4 host data[6] b dvd data[6] i 1 123 h_d_5 b4 host data[5] b dvd data[5] i 1 124 aud_bck b4 audio out bit clock o geniomis[3] b 125 h_d_4 b4 host data[4] b dvd data[4] i 1 126 vss_core gnd core ground 127 h_d_3 b4 host data[3] b dvd data[3] i 1 128 aud_lrck o4 audio out lr clock o 129 vdd_core pwr core power 2.5v 130 h_d_2 b4 host data[2] b dvd data[2] i 1 131 vdd_io pwr i/o power 3.3v 132 h_d_1 b4 host data[1] b dvd data[1] i 1 133 aud_do_2 b4 audio out data[2] o geniomis[2] b 134 h_d_0 b4 host data[0] b dvd data[0] i 1 135 aud_do_0 o4 audio out data[0] o 136 aud_do_1 b4 audio out data[1] o geniomis[1] b 137 ain_bck iu audio in bit clock i 138 vss_core gnd core ground 139 ain_lrck iu audio in lr clock i 140 ain_data b4u audio in data i geniomis[0] b 141 vdd_core pwr core power 2.5v 142 cdc_di iu serial codec data in i 143 vss_io gnd i/o gr ound 144 cdc_do t4 serial codec data out o 145 vin_clk iu video input clock i 146 cdc_rst t4 serial codec reset o 147 cdc_ck iu serial codec bit clock i 148 cdc_sy b4u serial codec sync b 149 gpio_v10 b4u geniomis[26] b 150 gpio_d15 b4u geniodvd[15] 151 gpio_d14 b4u geniodvd[14] 152 gpio_d13 b4su geniodvd[13] 153 vin_vsnc b4u video input vsync i geniomis[25] b 154 clk27_o b4u video output clock o geniomis[6] b 155 gpio_d12 b4u geniodvd[12] 156 vdd_pll pwr pll power 2.5v 157 vss_pll gnd pll ground table 6. pin assignments (continued)
CS98000 30 ds525pp1 158 vss_core gnd core ground 159 hsync b4u video output hsync o geniomis[4] b 160 vin_hsync b4u video input hsync i geniomis[24] b 161 vdd_core pwr core power 2.5v 162 vsync b4u video output vsync o geniomis[5] b 163 vdat_0 o4 video output data[0] o 164 vin_d0 b4u video input data[0] i geniomis[16] b 165 vdat_1 o4 video output data[1] o 166 vdat_2 o4 video output data[2] o 167 vdat_3 o4 video output data[3] o 168 vin_d1 b4u video input data[1] i geniomis[17] b 169 vdat_4 o4 video output data[4] o 170 vdat_5 o4 video output data[5] o 171 unused may leave unconnected 172 vdat_6 o4 video output data[6] o 173 vdat_7 o4 video output data[7] o 174 gpio_0 b4u general purpose io[0] b audio pll input bypass i 175 vin_d2 b4u video input data[2] i geniomis[18] b 176 vss_core gnd core ground 177 aud_do_3 b4u audio out data[3] o general purpose io[1] b 178 vdd_core pwr core power 2.5v 179 vin_d3 b4u video input data[3] i geniomis[19] b 180 vdd_io pwr i/o power 3.3v 181 gpio_2 b4u general purpose io[2] b 182 vss_io gnd i/o gr ound 183 gpio_3 b4u general purpose io[3] b 184 vin_d4 b4u video input data[4] i geniomis[20] b 185 gpio_4 b4u general purpose io[4] b 186 scl b4u i 2 c clock b general purpose io[5] b 187 sda b4u i 2 c data b general purpose io[6] b 188 gpio_7 b4u general purpose io[7] b 189 vin_d5 b4u video input data[5] i geniomis[21] b 190 gpio_8 b4u general purpose io[8] b 191 aud_xclk b4u audio 256x/384x clock b general purpose io[9] b 192 gpio_10 b4u general purpose io[10] b 193 vin_d6 b4u video input data[6] i geniomis[22] b 194 gpio_11 b4u general purpose io[11] b 195 gpio_12 b4u general purpose io[12] b 196 gpio_13 b4u general purpose io[13] b 197 gpio_14 b4u general purpose io[14] b 198 vin_d7 b4u video input data[7] i geniomis[23] b table 6. pin assignments (continued)
CS98000 ds525pp1 31 notes: 1. pin may be used for micro-less dvd loader interface 2. h_d(15:8) pins may be reassigned as geniohst(7:0) 6.2 miscellaneous interface pins these pins are used for used for basic functions such as clock and reset input. the i 2 c are used for both master and slave mode (8-bit slave address is 0x30 for write, and 0x31 for read). 6.3 sdram interface these pins are used to interface the CS98000 with some external sdram. the CS98000 can interface with sdram of various size. both 16 and 32 bit data width is supported, but best performance is achieved with 32 bits. follow instructions in the following ta- ble on how to interface any particular configuration of sdram. 6.4 rom/nvram interface this is the interface to the non-volatile memory that contains the firmware. it could be either rom, nvram C flash or eeprom - or any combina- tion of those. this interface can also connect to sram that would emulate a rom on a development system. the bus width is eight or 16 bits. except for the nvm_we_l and nvm_oe_l pins, all these pins are shared with the dram interface, which op- erates simultaneously with the rom/nvram inter- face. 199 gpio_15 b4u general purpose io[15] b 200 vss_core gnd core ground 201 ir_in is infrared input i 202 xtlclock i 27 mhz clock in i 203 vdd_core pwr core power 2.5v 204 spdif_o o4 s/pdif out o 205 rst_n is reset in i 206 mfg_test i (tie to ground) i 207 vin_fld id video input field 208 vss_pll gnd pll ground table 6. pin assignments (continued) pin signal name type description 186 scl b i 2 c clock 187 sda b i 2 c data 201 ir_in i infrared input, from ir receiver. 202 xtlclock i 27 mhz clock input. 205 rst_n i reset input, active low. 206 mfg_test i manufacturing test pin, should always connect to ground. table 7. miscellaneous interface pins
CS98000 32 ds525pp1 pin signal name type description 87, 83, 79, 76, 74, 71, 68, 64, 67, 70, 72, 75, 78, 80, 86, 88, 60, 56, 54, 49, 46, 44, 40, 33, 37, 42, 45, 48, 51, 55, 59. 62 m_d[31..0] b memory data bus. CS98000 can use all 32 bits or can use only m_d[15..0], in which case m_d[31..16] can be left un-con- nected. 2, 3, 5, 6, 7, 9, 10, 11, 13, 14, 15, 16 m_a[11..0] o memory address bus. connect in order starting with m_a[0] to all ram address pins not already connected to m_bs_l or m_ap. unused upper m_a pins unconnected. 19 m_cko o memory clock 22 m_cke o memory clock enable 21 m_bs_l o bank selection. always connect to ram bs or bs0 pin. 23 m_ap o memory auto pre-charge. always connect to ram ap pin. 24 m_ras_l o memory row address strobe 25 m_cas_l o memory column address strobe 27 m_we_l o memory write enable 32, 31, 29, 28 m_dqm[3..0] o io mask of data bus m_dqm[3] -> m_d[31:24] table 8. sdram interface pin signal name type description 60, 56, 54, 49, 46, 44, 40, 33, 37, 42, 45, 48, 51, 55, 59. 62 m_d[15..0] b memory data bus. use m_d[7:0] for 8-bit interface 2, 3, 5, 6, 7, 9, 10, 11, 13, 14, 15, 16 m_a[11..0] o memory address bus[11..0] 74, 71, 68, 64, 67, 70, 72, 75, 78, 80, 86, 88 m_d[27..16] o memory address bus[23..12] for 16-bit data mode, m_d[26:16] is upper word address. for 8-bit data mode, m_d[27:16] is upper byte address. 83 m_d[30] o address decode low. copy of address msb. 87 m_d[31] o address decode high. compliment of address msb. 60 nvm_we_l o nvram write enable. 62 nvm_oe_l o rom/nvram output enable. table 9. rom/nvram interface
CS98000 ds525pp1 33 6.5 video output interface this is the interface to a video encoder chip that will send the CS98000 video signals to a tv. the output format is either ccir-601 or ccir-656. the CS98000 supports both master and slave con- figuration. for ccir-656 mode, the CS98000 must be the sync master. in this case, the hsync and vsync pins can be redefined as gpios. 6.6 video input interface the CS98000 support ccir-601, cif and qcif video input format thought this interface. pin signal name type description 154 clk27_o o 27 mhz clock output. 159 hsync b horizontal sync. output when the CS98000 is the video master, input when the video encoder is master. 162 vsync b vertical sync. output w hen the CS98000 is the video mas- ter, input when the video encoder is master. 173, 172, 170, 169, 167, 166, 165, 163 vdat[7..0] o video data output[7..0] in cb,y,cr,y format. table 10. video output interface pin signal name type description 145 vin_clk i video input clock. 153 vin_vsnc i video input vertical sync. 160 vin_hsnc i video input horizontal sync. 207 vin_fld i video input clock. 198, 193, 189, 184, 179, 175, 168, 164 vin_d [7..0] i video data input[7..0] in cb,y,cr,y format. table 11. video input interface
CS98000 34 ds525pp1 6.7 audio output/input interface this is the audio pcm interface that connects to an audio codec. the sample rate and the size of the samples are programmable for both input and out- put direction. 6.8 ac97/codec interface this serial interface could be used either as a sec- ond pcm codec interface or as an ac97 serial link to an ac97 compliant codec. this could control a modem, or a second set of audio channels. pin signal name type description 191 aud_xclk b audio 256x/384x clock input or output to serial dac. when output, is generated from CS98000 internal pll. 124 aud_bck o audio bit clock output to serial dac. 128 aud_lrck o audio out left/right clock to serial dac. 135 aud_do_0 o audio serial data out[0]. 136 aud_do_1 o audio serial data out[1]. 133 aud_do_2 o audio serial data out[2]. 177 aud_do_3 o audio serial data out[3]. 204 spdif_o o s/pdif output 137 ain_bck i audio input bit clock. the CS98000 can be programmed to use the audio output functions internally generated bit clock, in which case this pin is not required. 139 ain_lrck i audio input left/right clock. the CS98000 can be pro- grammed to use the audio output functions internally gen- erated lr clock, in which case this pin is not required. 140 ain_data i audio input data from serial adc. table 12. audio output interface pin signal name type description 142 cdc_di i serial data input from modem codec 144 cdc_do o serial data output to modem codec 146 cdc_rst o reset output to modem codec 147 cdc_ck i serial bit clock input from modem codec 148 cdc_sy b frame sync, output when CS98000 is master, input when codec is master. table 13. ac97/codec interface
CS98000 ds525pp1 35 6.9 host master/atapi interface this 16 bits parallel host interface allows the CS98000 to be a host master, controlling other de- vices that would be used on the same system. the interface supports a programmable protocols and speeds, including multiplexed and non-multiplexed addressing. slaves with different protocols can be connected at the same time, controlled by different chip selects. 6.10 dvd i/o channel interface this interface connects to standard dvd loaders, and consists of three parts: control, dvd data and cd data. this interface shares CS98000 pins with the host master/atapi interface. the definition of the pins is set via register programming, and the two modes are mutually exclusive. 6.11 general purpose input/output (gpio) the CS98000 provides 37 gpio pins, each with in- dividual output tri-state controls. additional pins may also be re-defined and gpios. 6.12 power and ground the CS98000 requires 3 different types of power supplies C plls, internal logic and io pins -. the plls and internal logic use 2.5 v power supply, the io pins use 3.3 v power supply, and are 5 v input tolerant. pin signal name type description 111, 115, 101, 106 h_cs[3..0] o host chip select{3..0]. the host master can be pro- grammed to use a different protocol for each of the 4 chip selects 85 h_ale o host address latch enable. used for modes which multiplex upper address information onto the data lines 92 h_rd o host read request. 93 h_wr o host write request. 95 h_rdy i host ready. connect to pull-up or pull-down if host is not used. 120 h_cko o host clock out, required for some synchronous slaves 102, 107, 97, 99, 100 h_a[4..0] o host address[4..0]. 109, 110, 112, 113, 114, 116, 117, 118, 121, 122, 123, 125, 127, 130, 132, 134 h_d[15..0] b host data bus[15..0]. these pins can also output host address during the address phase for multiplexed address/data mode. tie together to pull-up or pull-down if host is not used. table 14. host master interface
CS98000 36 ds525pp1 pin signal name type description 121, 122, 123, 125, 127, 130, 132, 134 h_d[7:0] i dvd_data[7:0] C dvd data port parallel data input from loader 118 h_d[8] o control port clock to loader 117 h_d[9] i control port ready signal from loader 116 h_d[10] o control port serial command to loader 114 h_d[11] i control port serial status from loader 113 h_d[12] i cd error signal from loader 112 h_d[13] i cd clock from loader 110 h_d[14] i cd left/right clock from loader 109 h_d[15] i cd serial data from loader 106 h_cs_0 i dvd data start sector signal from loader 101 h_cs_1 i dvd data error signal from loader 95 h_rdy o dvd data ready signal to loader 93 h_wr i dvd data enable signal from loader 92 h_rd i dvd data clock from loader table 15. dvd i/o channel interface pin signal name type description 26, 17, 4, 12, 8, 150, 151, 152, 155, 65, 69, 73, 77, 61, 57, 50, 47, 43, 39, 34, 30 gpio_d[20:0] b 21 general purpose i/os 98, 94, 89 gpio_h[16:14] b 3 general purpose i/os 149 gpio_v10 b general purpose i/o 199, 197, 196, 195, 194, 192 gpio_[15:10] b 6 general purpose i/os 190, 188 gpio_[8:7] b 2 general purpose i/os 195, 183, 181 gpio_[4:2] b 3 general purpose i/os 174 gpio_0 b general purpose i/o table 16. general purpose i/o interface
CS98000 ds525pp1 37 pin signal name type description 1, 105, 158 vdd_pll 2.5v for internal plls 41, 66, 84, 108, 129, 141, 161, 178, 203 vdd_core 2.5v for internal core logic 20, 38, 91, 131, 180 vdd_io 3.3v for i/os 104, 157, 208 vss_pll ground for internal plls 36, 63, 82, 103, 126, 138, 158, 176, 200 vss_core gro und for internal core logic 18, 35, 58, 96, 119, 143, 182 vss_io ground for i/os table 17. power and ground
CS98000 38 ds525pp1 7. package specifications 1 52 53 104 105 156 157 208 0.50 0.05 0.22 0.05 30.6 0.2 28.00 0.05 28.00 0.05 30.6 0.2 detail a 0 ( min ) r0.20 1.3 0.1 r0.15 10 15 0.15 typ. 0.20 base metal with plating 0.15 typ. 0.50 0.1 5 0.2 (min) 0.35 0.1 detail a 3.35 0.05 3.80(max)
? notes ?

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